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Home : Equipment > Telecommunications Test P > PB200
Tektronix PB200 Bit Error Rate Test Set

Bit Error Rate Test Set

Product Status: New / Refurbished
List Price: $36,995
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Download project datasheet details pdf file  Download Datasheet
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SPECIFICATIONS

The PB200 is particularly suited to packet-based systems. It's ideal for component or sub-system development testing of TDMA, B-ISDN, FITL, ATM, Satellite modems and similar communications protocols.

The ability to generate a "Mixed Mode" data pattern allows flexibility in constructing many forms of test signals. Two separate programmable word memories of 16 to 256 Kbits in length allow the construction of a packet or cell that can consist of user-definable preamble, overhead and data. The PB200 data generator has one word memory that is used to define the overhead and preamble and a second word memory to define the data. Each memory can consist of a user-defined pattern or PRBS. The PB200 can also function as a fully featured non-packetized BERT.

Signal Analysis

For complete flexibility in signal analysis, the PB200 allows BER analysis on all, or only part, of the received digital information. Analysis can be performed on only the overhead, only the data or both overhead and data at the user's selection.

Unique packetBERT PB200 Features
The PB200 provides several unique features and capabilities that are not found on other BERT products in this class. The receiver has a clock/data deskew range of 32 ns and the ability to measure propagation delay. Along with the Auto Search setup capability, the receiver can automatically measure "eye-width" at user-selectable BERs and extrapolate BER from data accumulated over much shorter elapsed times than normally required. The transmitter can also generate a gapped clock.
 
  • Packet or Cell BER Testing
  • DC to 200 Mbits/s Data Rate, NRZ-1
  • 256 Kbits Programmable WORD, PRBS, 1's Density and Selectable Mixed Mode
  • Auto Search and Auto Sync Capability
  • Controllable Gapped Tx Clock
  • Automatic Eye-width Measurement and Extrapolation
  • Clock/Data Delay up to 32 ns in 20 ps Increments
  • Variable Data/Clock Amplitude and Offset Including ECL, PECL and High-Z TTL
  • Mixed-mode Testing
  • Pattern Editor Software for Custom Word Patterns (PC Windows-based)
AVAILABLE EQUIPMENT OPTIONS
None Available

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