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Keysight Technologies 1660C 136-CHNL BENCHTOP LOGIC ANAL
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SPECIFICATIONS
State and timing channels: 136 Setup/hold time: 3.5/0 ns to 0/3.5 ns State/timing memory depth: 4k on all channels, 8k on half channels Timing analysis modes and speeds (conventional): 250MHz on all channels, 500MHz on half channels Timing analysis modes and speeds (transitional): 125MHz on all channels, 250MHz on half channels Timing analysis modes and speeds (glitch): 125MHz on half channels State analysis speed: 100MHz Minimum detectable glitch width: 3.5 ns

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